1. Technical Field
The embodiments described herein relate to a semiconductor memory apparatus, and in particular, to a data output circuit that outputs data stored in a semiconductor memory apparatus.
2. Related Art
A conventional semiconductor memory apparatus receives serial data, converts the serial data into parallel data therein, and stores the converted parallel data. In addition, a conventional semiconductor memory apparatus converts the stored parallel data into serial data and outputs the converted serial data.
Accordingly, a conventional semiconductor memory apparatus includes a data output circuit that sequentially outputs the stored parallel data as the serial data.
FIG. 1 is a block diagram showing a general data output circuit for a conventional semiconductor memory apparatus.
If a read command “read_command” is input, the general data output circuit for a semiconductor memory apparatus generates output control signals “rpoutb<0:3>,” “fpoutb<0:3>,” and “poutb,” and converts parallel data “data_p<0:7>” into serial data “data_s<0:7>” in response to the output control signals “rpoutb<0:3>,” fpoutb<0:3>, and poutb. The data output circuit outputs the serial data “data_s<0:7>” in synchronization with a rising clock “rclk” and a falling clock “fclk.” At this time, the rising clock “rclk” has a high-level period at the rising edge of the external clock “clk,” and the falling clock “fclk” has a high-level period at the falling edge of the external clock “clk.”
The data output circuit includes a data bit selection control unit 10 and a clock-responsive data output unit 20.
If the read command “read_command” is input to the semiconductor memory apparatus, the data bit selection control unit 10 generates the output control signals “rpoutb<0:3>,” “fpoutb<0:3>,” and “poutb” in synchronization with the external clock “clk” (hereinafter, referred to as “clock”).
The clock-responsive data output unit 20 outputs the parallel data “data_p<0:7>” as the serial data “data_s<0:7>” in response to the output control signals “rpoutb<0:3>,” “fpoutb<0:3>,” and “poutb,” the rising clock “rclk,” and the falling clock “fclk.”
FIG. 2 is a timing chart of the general data output circuit for a semiconductor memory apparatus.
The general data output circuit receives the parallel data “data_p<0:7>” when the output control signal “poutb” is enabled at a low level.
The output sequence of the even-numbered data “data<0>,” “data<2>,” “data<4>,” and “data<6>” in the input parallel data “data_p<0:7>” is determined on the basis of an enable sequence of the output control signals “rpoutb<0:3>.” In addition, the output sequence of the odd-numbered data “data<1>,” “data<3>,” “data<5>,” and “data<7>” in the parallel data “data_p<0:7>” is determined on the basis of an enable sequence of the output control signals “fpoutb<0:3>.”
As a result, the general data output circuit for a semiconductor memory apparatus outputs the even-numbered data “data<0>,” “data<2>,” “data<4>,” and “data<6>” during a period in which the low enable period of each of the output control signals “rpoutb<0:3>” and the high-level period of the rising clock “rclk” overlap each other. In addition, the data output circuit outputs the odd-numbered data “data<1>,” “data<3>,” “data<5>,” and “data<7>” during a period in which the low enable period of each of the output control signals “fpoutb<0:3>” and the high-level period of the falling clock “fclk” overlap each other.
In the general data output circuit, in order to output the 8-bit parallel data “data_p<0:7>” stored in the semiconductor memory apparatus as the serial data “data_s<0:7>,” it is necessary to receive 11 signals in total, that is, the 9 output control signals “rpoutb<0:3>,” “fpoutb<0:3>,” and “poutb,” the rising clock “rclk,” and the falling clock “fclk.”
For this reason, in the known data output circuit, 11 signal lines are needed to output the data to the minimum. Due to a large number of signal lines, the area of the semiconductor memory apparatus is inevitably increased. When a skew occurs in the rising clock and the falling clock, the data may not be normally output.